The present invention relates to semiconductor manufacturing in general, and more specifically to a method for providing an improvement of an isolation structure in a non-volatile memory.
Non-volatile memory, which includes Mask Read-only memory (Mask ROM), Programmable Read-only memory (PROM), Erasable Programmable Read-only memory (EPROM), Electrically Erasable Programmable Read-only memory (EEPROM), and Flash memory, can keep stored information even when the electricity supply has been removed. Non-volatile memory is thus extensively used in the semiconductor industry and is another class of memories developed to prevent loss of programmed data. Typically, the manufacturer or user can program a non-volatile memory based on requirements, and the programmed data can be stored for a long time interval.
The IT market has grown quickly in the past decades. Portable computers and the electronic communications industry have become the main driving force for semiconductor VLSI design. As a result, low power consumption, high density and re-programmable non-volatile memory are in great demand. These programmable and erasable memories are able to store application programs and working systems, and they have become essential devices in the semiconductor industry.
A rising demand for memory function means higher requirements for integration level. Flash memory is advantageously multi-programmable and has become one of the fastest developing new generation memories. FIG. 1 is a schematic, top view of a conventional memory structure, which is a typical Twin Cell flame structure. A margin 6 surrounds contact 5 to prevent misalignment of contact 5. If contact 5 is misaligned and is not constructed in an anticipated position, contact 5 then falls within a region of margin 6. Margin 6 also serves as an isolation structure and thus prevents electrical shorts which would occur if contact 5 were able to conduct with nearby devices. Due to this ability to avoid a short, the entire circuit enjoys a better performance but the margin region blocks better integration in a semiconductor.
Improved integration of a semiconductor device results in a more powerful and higher performance device, and also in increased resistance in the source/drain regions. When the source/drain resistance equals the semiconductor device channel resistance, self-aligned silicide is usually used to reduce the sheet resistance of drain and source and assure complete function of a Shallow Junction between the metal and Metal-Oxide-Semiconductor (MOS) device. This is achieved by sputtering titanium on the structure surface and performing rapid thermal treatment so that the titanium and silicon react to form a good conductor. Excess titanium is removed by wet etching. Ideally, TiSi2 is only formed on the surface of the drain, source and gate. In a Twin Cell frame structure as depicted in FIG. 1, neighboring TiSi2 formed on a memory cell may interfere and create shorts with each other due to a lack of effective isolation therebetween. This lowers semiconductor performance.
In accordance with the preferred embodiment of the present invention, an improved non-volatile memory design resolves the problem of shorts between TiSi2 when a contact is misaligned.
It is one objective of the present invention to provide a space-saving manufacturing method for non-volatile memory. The margin region employed in prior art as isolation is unnecessary because a misalignment in the present invention does not result in a short. Reduction of the margin region also advantageously increases semiconductor device integration.
It is another objective of the present invention to provide a fabrication method in which short circuits between the gate, drain and source, and different transistors are prevented.
It is yet another objective of the present invention to provide a method in which no extra mask is needed and extra procedures and cost are avoided. In accordance with the foregoing and other objectives of the present invention, a manufacturing method for novel isolation in non-volatile memory is described. The method comprises providing a substrate with a plurality of Shallow Trench Isolation (STI) structures used for defining at least a local interconnected region and an active area. A tunnel oxide is then formed on the substrate and a first polysilicon layer and a first silicon nitride layer are sequentially deposited thereon. After locating the active area of the MOS, a Buried Drain and a Large Angle Tile Drain are formed in the substrate by ion implantation. A High-Density Plasma (HDP) oxide layer is then deposited on the substrate and partially removed to expose an upper edge of the first silicon nitride layer. A second silicon nitride layer is deposited on the HDP oxide layer. Portions of the second silicon nitride layer over the first silicon nitride layer are removed by CMP. The remaining second silicon nitride layer is removed by etching. Portions of HDP oxide layer on the first silicon nitride layer are also removed while etching the remaining second silicon nitride layer.
A second polysilicon layer is then formed on the first polysilicon layer and HDP oxide layer. The second polysilicon layer is partially removed by etching to expose the STI structures and the HDP oxide layer between two first polysilicon layers. A dielectric material (ONO) layer, a third polysilicon layer and a hard mask layer are formed sequentially over the substrate. The hard mask is patterned in a direction almost perpendicular to that of the first polysilicon layer. All exposed polysilicon material, including first, second and third polysilicon layers, and the exposed portions of the ONO layer are removed, leaving the remaining HDP oxide layer.
The exposed remaining HDP oxide layer serves as a mask while etching to form recesses in the substrate. Etching continues to remove all exposed remaining HDP oxide material on the substrate surface. A dielectric material layer is then deposited over the substrate and fills the recesses in the substrate. The dielectric material layer is then overetched to expose the substrate surface, thereby obtaining a spacer which extends from the recessed area to the hard mask layer.
After the spacer is formed, a conventional multi-layer semiconductor process, such as borderless contact or Salicide process, is subsequently performed.